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*The following are the basic parameters of the product, involving the characteristics of the product and its category
| TYPE | DESCRIPTION |
|---|---|
| Part Status | Active |
| RoHS Status | RoHS Compliant |
| Surface Mount | YES |
| Packaging | Tray |
| Terminal Form | GULL WING |
| Technology | CMOS |
| Factory Lead Time | 16 Weeks |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Number of Logic Blocks (LABs) | 24 |
| Terminal Pitch | 0.5mm |
| Terminal Position | QUAD |
| HTS Code | 8542.39.00.01 |
| Supply Voltage | 1.5V |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
| Peak Reflow Temperature (Cel) | 245 |
| Frequency | 80MHz |
| Length | 28mm |
| Width | 28mm |
| Core Architecture | ARM |
| Operating Temperature | 0°C~85°C TJ |
| Number of Terminations | 208 |
| Number of Pins | 208 |
| RAM Size | 64kB |
| Core Processor | ARM? Cortex?-M3 |
| Height Seated (Max) | 4.1mm |
| Architecture | MCU, FPGA |
| Peripherals | DMA, POR, WDT |
| Supply Voltage-Max (Vsup) | 1.575V |
| Package / Case | 208-BFQFP |
| Supply Voltage-Min (Vsup) | 1.425V |
| Flash Size | 512KB |
| Number of Equivalent Gates | 500000 |
| Series | SmartFusion? |
| Terminal Finish | Pure Matte Tin (Sn) |
| Primary Attributes | ProASIC?3 FPGA, 500K Gates, 11520 D-Flip-Flops |
| Connectivity | Ethernet, I2C, SPI, UART/USART |
| Base Part Number | A2F500M3G |
| Number of I/O | MCU – 22, FPGA – 66 |
| Interface | Ethernet, I2C, SPI, UART, USART |
| Organization | 11520 CLBS, 500000 GATES |
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