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*The following are the basic parameters of the product, involving the characteristics of the product and its category
| TYPE | DESCRIPTION |
|---|---|
| Part Status | Active |
| Radiation Hardening | No |
| RoHS Status | Non-RoHS Compliant |
| Surface Mount | YES |
| Number of Logic Blocks (LABs) | 8 |
| Factory Lead Time | 12 Weeks |
| Packaging | Tray |
| JESD-609 Code | e0 |
| Technology | CMOS |
| Time@Peak Reflow Temperature-Max (s) | 20 |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Published | 2009 |
| Terminal Pitch | 1mm |
| Terminal Position | BOTTOM |
| Frequency | 100MHz |
| Terminal Form | BALL |
| Operating Supply Current | 1mA |
| Supply Voltage | 1.5V |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
| Subcategory | Field Programmable Gate Arrays |
| Peak Reflow Temperature (Cel) | 225 |
| Core Architecture | ARM |
| Length | 23mm |
| Width | 23mm |
| Operating Temperature | -40°C~100°C TJ |
| Number of Terminations | 484 |
| Number of Pins | 484 |
| RAM Size | 64kB |
| Core Processor | ARM? Cortex?-M3 |
| Number of Outputs | 94 |
| Architecture | MCU, FPGA |
| Peripherals | DMA, POR, WDT |
| Supply Voltage-Max (Vsup) | 1.575V |
| Flash Size | 256KB |
| Package / Case | 484-BGA |
| Supply Voltage-Min (Vsup) | 1.425V |
| Height Seated (Max) | 2.44mm |
| Number of Gates | 200000 |
| Series | SmartFusion? |
| Connectivity | EBI/EMI, Ethernet, I2C, SPI, UART/USART |
| Interface | EBI/EMI, Ethernet, I2C, SPI, UART, USART |
| Base Part Number | A2F200 |
| Primary Attributes | ProASIC?3 FPGA, 200K Gates, 4608 D-Flip-Flops |
| Number of I/O | MCU – 41, FPGA – 94 |
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